A focal plane detector array comprises numerous detector unit cells or pixels, each of which converts incident electromagnetic radiation to an electric signal. The unit cells output an analog signal corresponding to scene radiation sensed by the particular detector element. These analog signals must be converted to digital in order to be combined and efficiently processed to resolve an image of a scene being viewed by the array of detector elements. It is noted that focal plane detector arrays are disposed within a temperature controlled chamber to minimize localized heat that might otherwise interfere with the intended scene radiation as noise. Excessive power dissipation, such as by power inefficient amplifiers and ADCs mounted in or near the chamber, places an additional burden on the Dewar or thermoelectric cooling elements that are employed for regulating chamber temperature.
Two types of ADCs have been found advantageous for use in imaging arrays: delta-sigma ADCs and residue readout ADCs. Delta sigma ADCs integrate the difference between an input signal and an output value. The integrator, typically an op-amp and a capacitor, is embedded in a feedback loop in such a way that the difference is driven to zero, making the output (a digital bit stream or word) equal in value to the voltage or current input. One example of a delta-sigma ADC is provided in FIG. 1 (prior art). The ADC of FIG. 1 is a first order delta-sigma ADC and includes a count and dump decimator, and is not configured to take advantage of the unipolar input. Note that the switch allows the reference value to be sent either to the sum or to the difference port of the summing function, enabling the circuit of FIG. 1 to follow both positive and negative signal inputs. Some of the advantages of this design include having a 20-bit capable ADC, without a requirement for a secondary ADC. However, this design typically requires a large counter that must be present in each ADC. Further, for a given frame time, the maximum signal to noise ratio (SNR) is constrained by the unit cell area, clock frequency, and power limitations. One difficulty with prior art delta-sigma circuits is that they generally employ an amplifier that consumes too much power for use in a large imaging array.
A modification of a first order delta-sigma ADC is the residue-readout ADC, sometimes referred to as an Eden ADC, shown generally in FIG. 2 (prior art). At the right of FIG. 2 is a necessary auxiliary ADC. The main advantage of the Eden ADC over a delta-sigma ADC is the presence of a residue readout [the node labeled V0 (residue)], which enables the use of a smaller counter for a given signal to noise ratio (SNR) requirement. The resolution of the Eden ADC can be set higher than permitted by the length of the counter because the residue information can be used to refine the digital output word. The residue readout feature permits the Eden ADC to be operated as a delta-sigma ADC or a folding ADC. The Eden ADC can also take advantage of a unipolar signal provided by pixels or unit cells by replacing the adding and subtracting of the reference seen in FIG. 1 with a single charge dump capacitor that decrements the integration capacitor by a known amount. The bottom plate of the dump capacitor Cdump may be connected to a reference voltage Vref2, but ground can be used when layout constraints exist. As in all switched capacitor circuits, the switches provide a path for clock feed through, which appears as input offset current in the output digital word. Non-overlapping clock phases must be used. Eden ADCs are disadvantaged for use in an imaging array in that they require relatively high power per unit cell, the need for sample and hold buffers for each unit cell to provide the signal to the auxiliary ADC, and a SNR that is constrained to a maximum by residue read-out and the unit cell area for most embodiments.
Typically, delta-sigma and Eden ADCs are generally disposed one per column (or row) of arrayed unit cells, rather than per unit cell, to alleviate some of the above disadvantages. Many implementations attempted have involved placement of an ADC on the column of the read-out integrated circuit (ROIC). At least one attempt has involved an effort to fit a high dynamic range ADC to every unit cell in an infra-red FPA. However, these implementations each use ADC architecture of the delta-sigma or Eden variety, requiring significant power to achieve the bandwidth for use in an imaging array. What is needed is a low power ADC, such as one that may be used for each unit cell in a large imaging array, without drawing excessive power and without adding thermal noise that would reduce sensitivity of the detector elements that operate within the temperature controlled chamber.